Title :
3-D compact model for nanoscale junctionless triple-gate nanowire MOSFETs
Author :
Holtij, Thomas ; Graef, Michael ; Kloes, Alexander ; Iñiguez, Benjamin
Author_Institution :
Competence Centre for Nanotechnol. & Photonics, Tech. Hochschule Mittelhessen, Giessen, Germany
Abstract :
A 3-D analytical and physics-based compact model for extremely scaled junctionless (JL) triple-gate nanowire (TG-NW) MOSFETs is presented. Based on Poisson´s equation and the conformal mapping technique, a compact solution for the electrostatics is derived in 3-D. A current expression is presented, which is continuous in all regions of device operation, and which takes into account the specific behavior of JL transistors. The model is compared versus measurement and simulated data of JL TG-NW MOSFETs, whereby the structural model parameters equal the values given by the fabricated devices. Important electrical parameters, such as threshold voltage VT, drain-induced barrier lowering (DIBL) and subthreshold slope S are worked out.
Keywords :
MOSFET; Poisson equation; conformal mapping; electrostatics; nanowires; semiconductor device models; 3D analytical compact model; DIBL; Poisson equation; conformal mapping technique; current expression; device operation regions; drain-induced barrier lowering; electrical parameters; electrostatics; extremely scaled JL TG-NW MOSFET; extremely scaled junctionless triple-gate nanowire MOSFET; nanoscale junctionless triple-gate nanowire MOSFET; physics-based compact model; structural model parameters; subthreshold slope; threshold voltage; Data models; Electric potential; Logic gates; MOSFET; Mathematical model; Semiconductor device modeling; DIBL; Junctionless nanowire MOSFET; analytical modeling; conformal mapping; sub-threshold slope; threshold voltage;
Conference_Titel :
Solid State Device Research Conference (ESSDERC), 2014 44th European
Conference_Location :
Venice
Print_ISBN :
978-1-4799-4378-4
DOI :
10.1109/ESSDERC.2014.6948809