Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application

A novel substrate-triggered grounded-gate NMOS (GGNMOS) is verified in 65 nm CMOS silicide process. The trigger element is a PMOS controlled by the VDD bus line and no other detection circuit is needed. Compared to traditional GGNMOS, with a 50 m trigger PMOS, the trigger voltage of the single finger structure can be reduced from 7.15 to 4.97 V and it also has lower overshoot voltage. Also the ultrathin gate oxide can be effectively protected, which is very important in nanometre circuits. For the multi-finger structure, with a 30 m trigger PMOS the proposed structure showed a 15.9 reduction in trigger voltage and a 13.5 increment as to failure current compared to traditional GGNMOS.