A new implant-through-contact method for fabricating high-voltage TFTs

Author

Huang, Tiao-Yuan ; Lewis, Alan G. ; Chiang, Anne ; Wu, I-Wei ; Koyanagi, Mitsumasa

Author_Institution

Xerox, Palo Alto, CA, USA

Volume

9

Issue

7

fYear

1988

fDate

7/1/1988 12:00:00 AM

Firstpage

347

Lastpage

349

Abstract

A process to fabricate offset-gate thin-film transistors for high-voltage (i.e. >60-V) large-area applications is demonstrated. In contrast to the conventional method where an additional masking step is applied to mask the channel and the offset regions, the n/sup +/ source-drain implant is performed in the present process only after contact is open, and is therefore self-aligned to the contact. The offset-gate transistors are achieved by proper transistor layout where the contact-to-gate distance equals the designed n/sup +/-to-gate offset. In addition to saving one masking count as compared with the conventional method, the implant-through-contact method also features a self-aligned field-plant structure and smaller transistor layout area.<>

Keywords

ion implantation; thin film transistors; high-voltage TFTs; implant-through-contact method; large-area applications; n/sup +/ source-drain implant; offset-gate thin-film transistors; self-aligned; self-aligned field-plant structure; transistor layout; transistor layout area; Circuits; Etching; Fabrication; Implants; Passivation; Resists; Strips; Thin film transistors; Topology;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.739

Filename

739