A VLSI chip mounting structure design based on computer simulation by HISETS

A VLSI chip mounting structure design method based on computer simulation by the Hitachi Semiconductor Thermal Strength Design System (HISETS) and some examples of simulated results are presented. In the analysis of multilayered chip mounting structures, the elastic, plastic, and creep behavior of bonding layers are taken into account by using HISETS. A good correspondence is found between simulated results and those obtained by testing. Simulated results show that, as VLSI chip size increases, (1) thermal conductance of the structure is improved; however, (2) the chip cracking safety factor, (3) the thermal cycle life of bonding layers, and (4) electrical resistance stability change negatively. For improving factors (2) to (4), it is effective to insert a buffer plate between the chip and its substrate. The appropriate thickness of the buffer plate depends on the desired specifications of the devices