A Receiver Architecture for Devices in Wireless Body Area Networks

A receiver architecture suitable for devices in wireless body area networks is presented. Such devices require minimum physical size and power consumption. To achieve this the receiver should, therefore, be fully integrated in state-of-the-art complementary metal-oxide-semiconductor (CMOS) technology, and size and power consumption must be carefully considered at all levels of design. The chosen modulation is frequency shift keying, for which transmitters can be realized with high efficiency and low spurious emissions. A direct-conversion receiver architecture is used to achieve minimum power consumption and a modulation index equal to two is chosen, creating a midchannel notch in the modulated signal. A tailored demodulation structure has been designed to make the digital baseband compact and low power. To increase sensitivity it has been designed to interface with an analog decoder. Implementation in the analog domain minimizes the decoder power consumption. Antenna design and wave propagation are taken into account via simulations with phantoms. The 2.45-GHz ISM band was chosen as a good compromise between antenna size and link loss. An ultra-low power medium access scheme has been designed, which is used both for system evaluation and for assisting system design choices. Receiver blocks have been fabricated in 65-nm CMOS, and a radio-frequency front-end and an analog-to-digital converter have been measured. Simulations of the complete baseband have been performed, investigating impairments due to 1/f noise, frequency and time offsets.