T4A: System-on-chip design using Tri-gate technology

At the cutting edge of silicon IC technology we have seen a move from the planar processes used for the last 50 years, to a new three dimensional approach to device design. State of the art production silicon at the 20nm process node uses silicon Tri-gate devices, and it is expected this will continue at the 14-16nm process geometry nodes. It is thus important to understand the specific design issues associated with system on chip circuit design using Tri-gate technology. This tutorial analyzes the design risks and benefits of using bulk tri-gate compared to conventional planar processes.