Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes

Author

Jaiswal, Ayush ; Walk, Dominik ; Yuan Fang ; Hofmann, Klaus

Author_Institution

Tech. Univ. Darmstadt, Darmstadt, Germany

fYear

2014

fDate

2-5 Sept. 2014

Firstpage

5

Lastpage

10

Abstract

A high-speed on-chip asynchronous Wave-pipelined (WP)-CMOS Serializer and Deserializer (SerDes) is superior to an on-chip synchronous CMOS SerDes in terms of power as it does not need power hungry synchronous circuits. Current Mode Logic (CML)-CMOS based SerDes achieves higher data-rate and throughput as CML logic can work at higher frequency. Therefore, a low-power on-chip asynchronous WP-CML SerDes structure is proposed. Simulation results in TSMC 65nm show that WP-CML SerDes is 55% faster than WP-CMOS implementation. In PVT sensitive environment, WP-CMOS SerDes (with -41.1%/+55.8% variations) cannot be used while WP-CML SerDes (with 9.3%/+8.6% variations) can work well with 10% timing margin.

Keywords

CMOS logic circuits; asynchronous circuits; current-mode logic; low-power electronics; PVT sensitive environment; WP-CMOS serializer-deserializer; current mode logic; data-rate; low-power high-speed on-chip asynchronous wave-pipelined CML SerDes; on-chip synchronous CMOS SerDes; timing margin; CMOS integrated circuits; Delays; Integrated circuit interconnections; Latches; Synchronization; System-on-chip; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip Conference (SOCC), 2014 27th IEEE International

Conference_Location

Las Vegas, NV

Type

conf

DOI

10.1109/SOCC.2014.6948891

Filename

6948891