Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video

With the increasing resolution of 3D high definition (HD) video, high bandwidth, large capability, low power memory becomes essential. In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with through-silicon-vias (TSVs), the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator, a global rank controller and local slice controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can improve bandwidth by 54.3% through command reordering and bank/rank interleaving. Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.