Design of a low power CMOS 10bit flash-SAR ADC

Author

Gi-Yoon Lee ; Kwang-Sub Yoon

Author_Institution

Dept. of Electron. Eng., Inha Univ., Incheon, South Korea

fYear

2014

fDate

2-5 Sept. 2014

Firstpage

88

Lastpage

91

Abstract

This paper proposed a low power CMOS flash-SAR ADC which consists of a flash ADC for 2 most significant bits and a SAR ADC with capacitor DAC for 8 least significant bits. Employment of a flash ADC allows the proposed circuit to enhance the conversion speed. The SAR ADC with a capacitor DAC provides a low power dissipation. The proposed ADC consumes 136 uW with a power supply of 1 V under a 0.18 um CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2 MHz. Therefore it results in 120 fJ/step of Figure of Merit (FoM).

Keywords

CMOS digital integrated circuits; analogue-digital conversion; capacitors; digital-analogue conversion; flip-flops; integrated circuit design; low-power electronics; CMOS process; FoM; analog-digital converter; capacitor DAC; conversion speed; figure of merit; low power CMOS flash-SAR ADC; power 136 muW; power supply; sampling frequency; size 0.18 mum; successive approximation register; voltage 1 V; Arrays; CMOS integrated circuits; Capacitors; Clocks; Logic circuits; Power demand; Power dissipation; Analog to Digital Converter; Flash ADC; Low power; SAR;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip Conference (SOCC), 2014 27th IEEE International

Conference_Location

Las Vegas, NV

Type

conf

DOI

10.1109/SOCC.2014.6948905

Filename

6948905