Temperature-Dependent Modeling and Characterization of Through-Silicon Via Capacitance

A semianalytical model of the through-silicon via (TSV) capacitance for elevated operating temperatures is derived and verified with electrical measurements. The effect of temperature on the increase in TSV capacitance over different technology parameters is explored, and it is shown that higher oxide thickness reduces the impact of temperature rise on TSV capacitance, while with low doped substrates, which are instrumental for reducing the TSV capacitance, the sensitivity of TSV capacitance to temperature is large and cannot be ignored.