A clock generator based on multiplying delay-locked loop

This paper presents a clock generator based on multiplying delay-locked loop (MDLL). With the aid of the frequency detector and the improved select logic circuitry, the clock generator can perform the lock-in process and the edge-selecting function correctly. It also provides the capability of the frequency switching like the conventional PLL-based clock generators without any external control signal. The test chip is designed and fabricated in TSMC 0.18 μm CMOS process. The core circuitry occupies an area of 0.06 mm² and consumes the power of 22.4 mW at the output frequency of 1.19 GHz. The measured peak-peak jitter is 19.2 ps.