A new design methodology for Voltage-to-Time Converters (VTCs) circuits suitable for Time-based Analog-to-Digital Converters (T-ADC)

Voltage-to-Time Converter (VTC) circuit is considered one of the essential blocks in the design of Time-based Analog-to-Digital Converters (T-ADCs). T-ADC is a promising candidate for Software Defined Radio (SDR) receivers that require wide band and high resolution ADC circuits. T-ADC circuits provide higher speed and lower power dissipation compared to conventional ADCs. The proposed design methodology increases the dynamic range of the VTC circuits. Moreover, the adoption of this new methodology results in increasing the VTC circuit sensitivity and improving the VTC linearity. In the proposed case study, the dynamic range increases up to 550mV with maximum linearity error of 3% and sensitivity of 2.13 ps/mV in TSMC 65nm CMOS technology, with a supply voltage of 1.2V.