PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems

On-chip regulators are becoming increasingly important for ultra-low voltage nano-scale SoC systems. In this paper, an all-digital controlled linear regulator is presented. A novel Process-Voltage-Temperature (PVT) -aware design is implemented to mitigate environmental variations and to guarantee the resolution of the liner regulator. The proposed digital voltage regulator can achieve up to 98.4% current efficiency. This design leads to three major advantages: (1) fast response time of 60ns, (2) low quiescent current 162μA in a stable state, and (3) PVT tolerance. The settling time is about 138ns. The output voltage error in 0.3V stable states with error improvement of the resolution using PVT-aware DED is around 50%. The best FOM at the regulated voltage (V_REG) of 0.51V is 4.2 pA·s. This digital controlled voltage regulator is designed and implemented for near-/sub- threshold operations. It can generate V_REG from 0.3V ~ 0.51V in steps of 30mV without resolution degradation under PVT variations. The total area of the regulator is about 388.6×35.7μm² using TSMC 65-nm low-power bulk CMOS technology.