MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs

In FinFETs, the back-gate of the transistor can be biased to control its V_th, thereby reducing leakage power at the expense of performance. This paper proposes a novel multi V_th dynamic logic design style (MITH-Dyn) which reduces the leakage power without degrading performance. MITH-Dyn has been tested on dynamic circuits of varying design complexity in both domino logic and np zipper logic. We report leakage savings of 90.83%, 89.14% and total power savings of 36.7%, 32.2% for domino circuits and np zipper circuits respectively. MITH-Dyn has also been extended to C²FinFET based latches and registers and also to NORA (No Race) FinFET based pipeline circuits. Total power savings of 27.98% and 36.16% was obtained for 2-stage and 4-stage NORA pipeline circuits respectively. We have used the 45nm FinFET model cards from PTM [1] for all the results reported in this paper.