Flow control solution for efficient communication and congestion avoidance in NoC

To achieve high performances at the application level in multiprocessor architecture MP-SoC, the NoC router should implement per flit handling strategy with high quality. This purpose requires an enhanced internal architecture that ensures from one hand a specific management according to a service classification and from the other hand, it enhances the routing process. In this context, this paper proposes a new mechanism for QoS management in network on chip. This mechanism is based on the use of central memory where flits are in-queued according to their class of service. This scheme enables an optimal flit scheduling phase and provides more capabilities to drop low important flits when the router shows congestion state symptoms. The paper presents, also, a protocol structure that fills with this architecture and introduces a signaling mechanism to make efficient the QoS management through the proposed architecture. The circuit performances and its adaptability to achieve quality of service with low power processing and high bandwidth in on chip multiprocessor systems will be studied in this paper.