Analysis of parasitic effects in triple-well CMOS SPDT switch

A comparison between a conventional body floating single pole double throw (SPDT) CMOS switch design and a proposed switched gate floating CMOS SPDT switch design based on an analysis of parasitic effects is presented. In standard CMOS technology, the switched gate floating switch is analytically proved to have higher isolation owing to the alleviation of parasitic diode and substrate coupling effects in the operation state. The proposed switch maintains a similar insertion loss as conventional switches while achieving an average of 6 dB isolation improvement over the operating frequency, which agrees well with the presented analysis.