An accelerated successive approximation technique for analog to digital converter design

This paper presents a novel technique to reduce the power consumption and potentially improve the conversion speed of successive approximation register (SAR) ADCs. Conventional SAR ADCs use binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed approach, referred to as accelerated-SAR, is capable of updating both the lower and upper bounds during a single conversion cycle. Even in cases that it can only update one bound, the proposed technique updates the bound more aggressively during the conversion. Logic circuits to execute the accelerated-SAR operation are developed. The proposed techniques are implemented in a 0.5V 10-bit ADC. Simulation results are presented to validate the proposed techniques.