Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

Author

Bock, Karlheinz ; Russ, Christian ; Badenes, Goncal ; Groeseneken, Guido ; Deferm, Ludo

Author_Institution

IMEC, Leuven B-3001, Belgium

Volume

21

Issue

4

fYear

1998

Firstpage

286

Lastpage

294

Abstract

An electrostatic discharge (ESD) evaluation of a silicided 0.25 μm complementary metal-oxide-semiconductor (CMOS) technology is carried out by HBM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices.

Keywords

encapsulation; flip-chip devices; integrated circuit reliability; integrated circuit yield; microassembling; FCOB; assembly costs; assembly yield; capillary action; chip placement; chip placement forces; compression flow modeling; cycle time; deposition geometry; direct chip attach; direct interconnection; flip-chip assembly; flip-chip on board; flow simulation studies; organic substrates; reliability; squeeze flow technique; surface topologies; underfill encapsulants; Assembly; Costs; Encapsulation; Geometry; Integrated circuit interconnections; Integrated circuit reliability; Integrated circuit technology; Materials reliability; Polymers; Solid modeling; CDM; ESD; HBM; TLP; deep-submicron; fully silicided; gate length; influence; performance; repetitive TLP; technology; well profile;

fLanguage

English

Journal_Title

Components, Packaging, and Manufacturing Technology, Part C, IEEE Transactions on

Publisher

ieee

ISSN

1083-4400

Type

jour

DOI

10.1109/3476.739178

Filename

739178