An energy efficient wireless Network-on-Chip using power-gated transceivers

Networks-on-Chip (NoCs) have been accepted as scalable and efficient communication backbone for many-core Systems-on-Chip (SoCs) by both the academia and the industry. However, the traditional approaches of implementing a NoC with planar metal interconnects have high latency and significant power consumption overhead. This is mainly due to the multi-hop links used in data exchange, specifically when the number of cores is significantly high. To address these problems, multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the energy efficient design of wireless NoCs using suitable on-chip wireless transceivers. Wireless transceivers with power gating can significantly improve the energy efficiency of the network. In this paper, we have implemented and evaluated sleep transistor based power-gated transceiver along with power-gating controlling unit for low power on-chip wireless interconnects. Design considerations for augmenting this technique with different wireless NoC architectures and corresponding overheads are also presented.