Reliability aware logic synthesis through rewriting

The low reliability of advanced CMOS devices has become a critical issue that has to be considered in the digital IC design flow. This paper introduces a design time methodology to address and improve the reliability of combinational circuits. The key idea is to employ local transformation rules, a methodology that were extensively used for area, delay, and power optimizations and demonstrate that they can reduce the error probability as well.We propose a set of local transformation rules that enhance the reliability without altering the circuit functionality. This functional rewriting capability, along with a circuit reliability assessment methodology developed in house, enables the integration of the reliability aware analysis and logic optimization algorithm that iteratively transforms the design in order to achieve higher circuit reliability. Experimental results based on simulations performed on MCNC benchmark circuits indicate that method can provide a reliability improvement of up to 7.5%.