REFLEX: Reconfigurable logic for entropy extraction

True Random Number Generators are cryptographic primitives that harness on-chip physical phenomena to generate random bits. Variations in the fabrication process and operating conditions can decrease reliability of these circuits by decreasing the randomness of their output. Conventional lightweight post-processing techniques use an XOR tree to combine the outputs of two or more TRNGs and improve the net entropy. We present REFLEX: Reconfigurable Logic for Entropy Extraction; a post-processing technique using reconfigurable logic. REFLEX replaces each stage of XOR tree with a reconfigurable logic block that is programmed based on the entropy of TRNGs. The output of TRNGs are further reordered before entering the logic tree to provide optimal entropy extraction. Up to 55% more chips pass NIST randomness tests when using REFLEX as compared to conventional XOR tree. When implemented in IBM 32nm SOI process, REFLEX has a maximum synthesized area of 620μm². It consumes a leakage power of 70μW and an energy overhead of 0.04pJ/bit when operating at 2GHz. The design is scalable to multiple TRNGs and provides energy efficient entropy extraction for low power applications.