DocumentCode
146312
Title
Emerging memristor technology enabled next generation cortical processor
Author
Hai Li ; Miao Hu ; Xiaoxiao Liu ; Mengjie Mao ; Chuandong Li ; Shukai Duan
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA
fYear
2014
fDate
2-5 Sept. 2014
Firstpage
377
Lastpage
382
Abstract
The explosion of “big data” applications imposes severe challenges of data processing speed and scalability on traditional computer systems. However, the performance of von Neumann machine is greatly hindered by the increasing performance gap between CPU and memory (“known as memory wall”), motivating the active research on new or alternative computing architecture. As one important instance, neuromorphic computing systems have gained considerable attentions. Neuromorphic computing systems refer to the computing architecture inspired by the working mechanism of human brains. The human neocortex system naturally possesses a massively parallel architecture with closely coupled memory and computing as well as the unique analog domain operations. By imitating such structure, neuromorphic computing system is anticipated to be superior to the conventional computer systems in image recognition and natural language understanding. Among all the possible solutions, cortical processor has gained significant attention. The cortical-like hierarchical model conducts data processing by using spatial and temporal evolution of the data representation to form relationships. The straightforward hardware realization of such massively parallel algorithms inspired by cortical models, however, commonly consumes a large volume of memory and computing resources, incurring high design complexity and hardware cost. Here, we suggest realizing the cortical processor by combining the flexibility of conventional architecture in computation and the efficiency of the emerging memristor technology. Computing accelerator is introduced to accelerate neuromorphic computations with ultra-low energy consumption. The computation and data exchange are carefully coordinated and supported by a hierarchical network-on-chip across digital and analog domains.
Keywords
Big Data; brain; medical computing; memristors; network-on-chip; neurophysiology; analog domain operations; big data; closely coupled memory; computing accelerator; cortical-like hierarchical model; data representation; hierarchical network-on-chip; human brains; human neocortex system; image recognition; massively parallel architecture; memory wall; memristor technology; natural language understanding; neuromorphic computing systems; next generation cortical processor; temporal evolution; ultra-low energy consumption; von Neumann machine; Arrays; Hardware; Memristors; Neuromorphics; Neurons; Training;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip Conference (SOCC), 2014 27th IEEE International
Conference_Location
Las Vegas, NV
Type
conf
DOI
10.1109/SOCC.2014.6948958
Filename
6948958
Link To Document