Title :
A hardware acceleration scheme for memory-efficient flow processing
Author :
Xin Yang ; Sezer, Sakir ; O´Neill, Shane
Author_Institution :
ECIT Inst., Queen´s Univ. Belfast, Belfast, UK
Abstract :
This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet.
Keywords :
DRAM chips; Internet; content-addressable storage; field programmable gate arrays; table lookup; telecommunication traffic; DDR3 SDRAM; Ethernet; FPGA; Internet traffic flows; hardware acceleration; memory efficient flow processing; network flow processing; packet header fields; packet throughput; Bandwidth; Computer aided manufacturing; Field programmable gate arrays; Hardware; Matched filters; SDRAM; Table lookup; content addressable memory; flow lookup table; hash; network flow processing;
Conference_Titel :
System-on-Chip Conference (SOCC), 2014 27th IEEE International
Conference_Location :
Las Vegas, NV
DOI :
10.1109/SOCC.2014.6948969
