A body-bias based current sense amplifier for high-speed low-power embedded SRAMs

Advances in CMOS technology has resulted in ever growing demand in on-chip high-density low-power SRAMs. A miniaturized low voltage-operated SRAM cell ability to generate adequate swing on heavily loaded bitlines is a serious design concern. In addition, Process, Voltage and Temperature variation PVTs in nanometric CMOS regime results in significant SARM cell parameters deviation. Sense amplifier offset voltage is the bottleneck in successful SRAM read operation. Therefore, offset voltage-insensitive current sense amplifiers are usually adopted in high performance SARMs. Read-assist techniques start to merge in the sate-of-the-art high-speed low-power SRAMs. This work presents a new high speed low power current sense amplifier. The proposed scheme utilizes transistor body bias to control the bitlines differential current. Monte Carlo simulations are conducted to validate the proposed scheme performance in presence of PVTs variations. Compared to conventional schemes, up to 28% in read failures reduction at 25mV bitlines swing is achieved. In addition, a 41% improvement in speed and up to 2.5X times less bitlines swing requirement at 0.6 V operating voltage is also verified.