DocumentCode :
1463559
Title :
An efficient architecture for two-dimensional discrete wavelet transform
Author :
Wu, Po-Cheng ; Chen, Liang-Gee
Author_Institution :
Inf. Technol. Div., Inst. for Inf. Ind., Taiwan, China
Volume :
11
Issue :
4
fYear :
2001
fDate :
4/1/2001 12:00:00 AM
Firstpage :
536
Lastpage :
545
Abstract :
This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform module, we employ the polyphase decomposition technique and the coefficient folding technique to the decimation filters of stages 1 and 2, respectively. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are 100% hardware utilization, fast computing time (0.5-0.67 times of the parallel filters´), regular data flow, and low control complexity, making this architecture suitable for next generation image compression systems, e.g., JPEG-2000
Keywords :
VLSI; data compression; digital signal processing chips; discrete wavelet transforms; image coding; multiplexing equipment; parallel architectures; random-access storage; transform coding; 2D DWT architecture; 2D discrete wavelet transform; JPEG-2000; RAM module; VLSI; coefficient folding; decimation filters; efficient architecture; fast computing time; hardware utilization; image compression systems; low control complexity; multiplexer; parallel filter architecture; polyphase decomposition; regular data flow; transform module; Computer architecture; Concurrent computing; Control systems; Data flow computing; Discrete transforms; Discrete wavelet transforms; Filters; Hardware; Multiplexing; Two dimensional displays;
fLanguage :
English
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8215
Type :
jour
DOI :
10.1109/76.915359
Filename :
915359
Link To Document :
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