DocumentCode
1463709
Title
Limits of integrated-circuit manufacturing
Author
Doering, Robert ; Nishi, Yoshio
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
Volume
89
Issue
3
fYear
2001
fDate
3/1/2001 12:00:00 AM
Firstpage
375
Lastpage
393
Abstract
A methodology is suggested for the study of integrated-circuit manufacturing limits. It is based on a hierarchical view of manufacturing detractors and associates limits with levels in this hierarchy. The methodology is illustrated with examples of steady-state, theoretical, and process limits at today´s state of the art as well as example projections to future manufacturing at what may be near the limits of complementary metal-oxide-semiconductor (CMOS) scaling. There are also some speculations on possibilities beyond these limits
Keywords
CMOS integrated circuits; integrated circuit manufacture; reviews; CMOS scaling; IC manufacturing limits; integrated circuit manufacturing; process limits; CMOS process; Circuits; Costs; Instruments; Manufacturing processes; Material properties; Pulp manufacturing; Semiconductor device manufacture; Semiconductor devices; Steady-state;
fLanguage
English
Journal_Title
Proceedings of the IEEE
Publisher
ieee
ISSN
0018-9219
Type
jour
DOI
10.1109/5.915380
Filename
915380
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