• DocumentCode
    1463727
  • Title

    Performance of PLL synthesiser based on DDS feedback

  • Author

    Brennan, Paul V. ; Walkington, R.

  • Author_Institution
    Dept. of Electron. & Electr. Eng., Univ. Coll. London
  • Volume
    34
  • Issue
    23
  • fYear
    1998
  • fDate
    11/12/1998 12:00:00 AM
  • Firstpage
    2197
  • Lastpage
    2199
  • Abstract
    An unusual phase-locked synthesiser architecture is described which is capable of agile operation with very good frequency resolution. Analyses are presented to show the fundamental limits of operation in terms of resolution, discrete spurii and phase noise floor
  • Keywords
    circuit feedback; direct digital synthesis; phase locked loops; DDS feedback; PLL synthesiser; discrete spurii; frequency agility; frequency resolution; phase noise; phase-locked loop;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19981512
  • Filename
    739582
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1463727