Computing inductive noise of CMOS drivers

The inductive noise (i.e., ΔI noise, simultaneous switching noise, or ground bounce) developed between the ground plane in the chip and the ground plane in the printed wiring board (PWB) seriously limits the number of on-chip drivers or bits that can be switched simultaneously in the same direction. This is especially the case for the ubiquitous complementary metal-oxide-semiconductor (CMOS) technology, which now forms the basis of VLSI. This paper presents a new electrical model for computing inductive noise associated with CMOS technology. The model is especially useful for computing inductive noise during chip-to-chip communication when n CMOS drivers are switched in the same direction at an arbitrary, monotonic set of times {t₁=0, t₂, t₃, ···, t_n} to form controlled skewing sequences