DocumentCode :
1464088
Title :
VLSI interconnect design automation using quantitative and symbolic techniques
Author :
Simunic, Tajana ; Rozenblit, Jerzy W. ; Brews, John R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Volume :
19
Issue :
4
fYear :
1996
fDate :
11/1/1996 12:00:00 AM
Firstpage :
803
Lastpage :
812
Abstract :
This paper presents a framework for design automation of VLSI interconnect geometries. Crosstalk, overshoot, undershoot, signal delay, and line impedance are design performance parameters under consideration. Since the dependence of electrical performance parameters on geometry is not easily defined, both qualitative and quantitative techniques are used. Two knowledge bases are introduced-a model and simulation base. The model base contains models used for terminations, transmission line parameter extractors, and transmission lines. The simulation knowledge base contains a set of approximations and routines for the exact evaluation of electrical performance parameters. Procedures are introduced for the automatic extraction of applicable models and simulation techniques in the design process. An unconstrained optimization routine is used as a design search technique. The approach presented here gives faster results than approaches shown in literature, with little sacrifice of accuracy
Keywords :
VLSI; circuit CAD; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; VLSI interconnect; crosstalk; design automation; electrical performance; knowledge base; line impedance; model; optimization; overshoot; parameter extraction; quantitative technique; search technique; signal delay; simulation; symbolic technique; termination; transmission line; undershoot; Crosstalk; Delay lines; Design automation; Design optimization; Geometry; Impedance; Process design; Signal design; Transmission lines; Very large scale integration;
fLanguage :
English
Journal_Title :
Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on
Publisher :
ieee
ISSN :
1070-9894
Type :
jour
DOI :
10.1109/96.544372
Filename :
544372
Link To Document :
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