Optimization of resistively hardened latches

The design of digital circuits tolerant to single-event upsets is considered. The results of a study in which an analytical model was used to predict the behavior of a standard resistively hardened latch are presented. It is shown that a worst-case analysis for all possible single-event upset situations (on the latch or in the logic) can be derived from studying the effects of a transient distributed write cycle. The existence of an intrinsic minimum write period to tolerate a transient of a given duration is also demonstrated. This minimum write period cannot be attained without proper resistor selection resulting from a complete optimization study. Analytic results are in sufficiently good agreement with SPICE results to guide simulation choices efficiently, and the model made it possible to develop a set of linear equations that allow the quick optimization of the studied latch for any transient durations and any IC CMOS processes