Design methodology and size limitations of submicrometer MOSFETs for DRAM application

A design methodology of submicrometer MOSFETs for a one-transistor DRAM cell is proposed, taking into account physical limiting phenomena such as (1) avalanche breakdown at the drain junction, (2) bulk punchthrough, (3) short-channel effect, and (4) hot-electron effect, and circuit-performance requirements such as (5) leakage current, (6) access delay, (7) noise margin and (8) α-particle-induced soft error. It has been found that a minimum metallurgical channel length is 0.42 μm at a circuit voltage of 2.8 V for a planar cell structure. Although these parameters are derived assuming a planar cell, the presented design method can be applied to advanced cell structures, such as stacked and trench cell structures, by setting adjustable design parameters for the area and capacitor factors of a memory cell