A 0.1–0.3 V 40–123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters

Author

Ho, Yingchieh ; Su, Chauchin

Author_Institution

Electr. Eng. Dept., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

47

Issue

5

fYear

2012

fDate

5/1/2012 12:00:00 AM

Firstpage

1242

Lastpage

1251

Abstract

This paper presents a 40-130 fJ/bit/ch on-chip data link design under a 0.1-0.3 V power supply. A bootstrapped CMOS repeater is proposed to drive a 10 mm on-chip bus. It features a -V_DD to 2V_DD swing to enhance the driving capability and reduces the sub-threshold leakage current. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. A test chip is fabricated in a 55 nm SPRVT Low-K CMOS process. The measured results demonstrate that for a 10 mm on-chip bus, the achievable data rate is 0.8-100 Mbps, and the energy consumption is 40-123 fJ per bit under 0.1-0.3 V V_DD.

Keywords

CMOS integrated circuits; bootstrap circuits; data communication; integrated circuit design; interference suppression; intersymbol interference; jitter; leakage currents; radiofrequency interference; repeaters; system-on-chip; ISI jitter; ISI-suppressed bootstrapped CMOS repeaters; SPRVT low-K CMOS process; data transmission; driving capability; energy consumption; leakage current reduction technique; on-chip bus; on-chip data link; precharge enhancement scheme; size 10 mm; size 55 nm; subthreshold leakage current; test chip fabrication; voltage 0.1 V to 0.3 V; Boosting; Leakage current; Logic gates; Noise; Repeaters; System-on-a-chip; Threshold voltage; Bootstrapped circuit; energy efficient; inter-symbol interference (ISI); leakage current reduction low-power; low-voltage; sub-threshold circuit;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2012.2186722

Filename

6165387