DocumentCode
1464734
Title
Characterization of layout dependent thermal coupling in SOI CMOS current mirrors
Author
Tenbroek, Bernard M. ; Redman-White, William ; Lee, Michael S L ; Bunyan, R. John T ; Uren, Michael J. ; Brunson, Kevin M.
Author_Institution
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
Volume
43
Issue
12
fYear
1996
fDate
12/1/1996 12:00:00 AM
Firstpage
2227
Lastpage
2232
Abstract
A current mirror is proposed as a suitable structure for the characterization of layout dependent thermal coupling between MOSFETs. Using current and voltage measurements, and compensating for series resistance effects, very small changes in local device temperature can be made visible. For the first time it is demonstrated that thermal coupling can be observed in a 2 μm SOI CMOS technology, with devices separated by as much as 20 μm. Measurements were verified by electro-thermal SPICE simulations, using a simple lumped model to express thermal coupling. The observations reinforce the need for accurate circuit level models, including self heating and thermal coupling effects, for analogue applications in VLSI SOI CMOS technologies
Keywords
CMOS analogue integrated circuits; VLSI; equivalent circuits; integrated circuit layout; integrated circuit measurement; integrated circuit modelling; silicon-on-insulator; thermal analysis; 2 micron; MOSFETs; SOI CMOS current mirrors; SOI CMOS technology; Si; VLSI technologies; analogue applications; characterization structure; current measurements; electro-thermal SPICE simulations; layout dependent thermal coupling; local device temperature changes; lumped model; self heating effects; series resistance effects compensation; voltage measurements; CMOS technology; Circuit simulation; Coupling circuits; Electrical resistance measurement; MOSFETs; Mirrors; SPICE; Semiconductor device modeling; Temperature; Voltage measurement;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.544395
Filename
544395
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