A 3.5 in 230 Mbytes read-channel chip set for magneto-optical disk drives

A read-channel chip set for rewritable 3.5 in 230 Mbytes magneto-optical disk drives (MOD) is presented. The front-end chip includes an automatic gain control (AGC) circuit, a programmable six-pole two-zero equiripple filter/equalizer, a DC restore circuit, and pulse detectors. The back-end contains a frequency synthesizer phase-locked loop (PLL) and a data separator PLL with 3:1 operating range to support a constant density recording with 8-24 Mb/s data rate (or code rate of 16 to 48 Mb/s) in (2, 7) run-length limited (RLL) encoding format. The architecture of the chip provides high degree of programmability through a serial microprocessor interface, fast switching (<1 /spl mu/s) between sector mark and data detector modes, and four levels of power management in a 1.5 /spl mu/m 4 GHz BiCMOS process. With a nominal power supply of 5 V, the chip set dissipates 600 mW during normal operation and 1 mW during sleep mode.