DocumentCode :
1464855
Title :
CMOS design of the tree arbiter element
Author :
Josephs, Mark B. ; Yantchev, Jelio T.
Author_Institution :
Centre for Concurrent Syst. & VLSI, South Bank Univ., London, UK
Volume :
4
Issue :
4
fYear :
1996
Firstpage :
472
Lastpage :
476
Abstract :
An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact design for the tree arbiter element which offers eager forward-propagation of requests. It compares favorably with a well-known design in which request propagation must wait for arbitration to complete. Our analysis and simulations also suggest that no performance improvement will be obtained by incorporating eager acknowledgment of releases. All of the designs considered in this paper are speed-independent, a formal property of a network of elements which can be taken as a positive indication of their robustness.
Keywords :
CMOS logic circuits; asynchronous circuits; flip-flops; integrated circuit design; logic design; resource allocation; CMOS design; asynchronous arbiter; dynamical resource allocation; glitch-free operation; multiway arbitration; request-grant-release-acknowledge protocol; tree arbiter element; two-way arbiters; Analytical models; CMOS technology; Joining processes; Performance analysis; Protocols; Resource management; Robustness;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.544412
Filename :
544412
Link To Document :
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