Projecting lifetime of deep submicron MOSFETs

Author

Li, Erhong ; Rosenbaum, Elyse ; Tao, Jiang ; Fang, Peng

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

Volume

48

Issue

4

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

671

Lastpage

678

Abstract

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I_b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons

Keywords

MOSFET; annealing; electron traps; hot carriers; semiconductor device reliability; 0.1 micron; 0.25 micron; channel length; deep submicron MOSFETs; device lifetime; energetic electrons; hot-carrier-induced degradation; interface depassivation; interface trap generation; operating voltage; oxide thickness; post-metallization anneal; primary degradation mechanism; stress voltage; worst case stress condition; Annealing; Degradation; Deuterium; Electron traps; Hot carriers; Life estimation; MOSFETs; Space technology; Stress; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.915682

Filename

915682