Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits

Author

Jiao, Hailong ; Kursun, Volkan

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

Volume

20

Issue

4

fYear

2012

fDate

4/1/2012 12:00:00 AM

Firstpage

741

Lastpage

745

Abstract

A new threshold voltage tuning methodology is explored in this paper to minimize the peak power/ground bouncing noise with smaller sleep transistors in multi-threshold CMOS (MTCMOS) circuits. Different circuit techniques with the threshold voltage tuning strategy lower the activation noise, the activation delay, and the size of the additional sleep transistors by up to 27.76%, 32.66%, and 85.71%, respectively, as compared to a previously published noise-aware MTCMOS circuit with standard zero-body-biased high threshold voltage sleep transistors in a UMC 80-nm CMOS technology.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit noise; UMC CMOS technology; activation delay; activation noise; multithreshold CMOS circuit; noise-aware MTCMOS circuit; peak power-ground bouncing noise; size 80 nm; threshold voltage tuning strategy; trimode MTCMOS circuits; zero-body-biased high threshold voltage sleep transistors; CMOS integrated circuits; Delay; Noise; Power demand; Threshold voltage; Transistors; Tuning; Activation delay; SLEEP to ACTIVE mode transition noise; forward body bias; leakage power;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2011.2110663

Filename

5723782