Title :
On-chip testing of embedded p.l.a.s
Author :
Varma, P. ; Ambler, A.P. ; Baker, K.
Author_Institution :
University of Manchester Institute of Science and Technology, Manchester, UK
fDate :
9/1/1985 12:00:00 AM
Abstract :
Rising test generation costs, compounded by the problem of module inaccessibility, have led to a surge of interest in self-testing methods for p.l.a.s. This paper considers the problems associated with the on-chip testing of p.l.a.s deeply embedded in v.l.s.i. systems and presents a method of on-chip testing which uses the input/output registers of the p.l.a. as test aids. An 8-input ×45 product term ×6-output built-in testable p.l.a., which has been implemented in n.m.o.s., is described.
Keywords :
VLSI; automatic testing; cellular arrays; integrated circuit testing; integrated logic circuits; logic testing; NMOS; PLAs; VLSI; input/output registers; module inaccessibility; on-chip testing; programmable logic arrays; self-testing methods; test generation;
Journal_Title :
Electronic and Radio Engineers, Journal of the Institution of
DOI :
10.1049/jiere.1985.0101
