Title :
A simulator for at-speed robust testing of path delay faults in combinational circuits
Author :
Hsu, Yuan-Chieh ; Gupta, Sandeep K.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fDate :
11/1/1996 12:00:00 AM
Abstract :
Conditions are derived for robust testing of a path delay fault via a sequence of vectors applied at-speed. A simulator has been developed that uses the above conditions, along with the knowledge of paths that are robustly tested by the previous vectors, to determine the fault coverage obtained by such testing. The results demonstrate that the existing fault simulators can overestimate robust path delay fault coverage by 5-15%
Keywords :
combinational circuits; delays; digital simulation; logic testing; at-speed robust testing; combinational circuits; fault coverage; path delay faults; simulator; Application software; Circuit faults; Circuit simulation; Circuit testing; Clocks; Combinational circuits; Delay; Electrical fault detection; Fault detection; Robustness;
Journal_Title :
Computers, IEEE Transactions on
