n-channel MOSFET breakdown characteristics and modeling for p-well technologies

A model of n-channel MOSFET breakdown, in a p-well, is proposed based on experimental measurements. The model identifies three parasitic bipolar transistors that generate two independent breakdown paths. The breakdown path is dependent on the biasing conditions, the relative parasitic bipolar transistor gain, and the drain avalanche breakdown. Typical biasing of the n-channel MOSFET will result in a breakdown path, and hence snapback sustaining voltage, which is a function of the gate length. While this result is similar to that found in previous studies of snapback on bulk substrates, there is an additional component of current present at the source due to the parasitic vertical bipolar transistor created by the p-well. Another separate parasitic vertical bipolar transistor can lead to an alternative breakdown path when the n-substrate is grounded or left floating. This alternative breakdown path is independent of the gate length for long channel lengths and dependent for short channel lengths. Experimental data and characterization results are presented from two Harris 5-V CMOS processes