Gate Tunneling in Nanowire MOSFETs

Author

Cao, W. ; Shen, C. ; Cheng, S.Q. ; Huang, D.M. ; Yu, H.Y. ; Singh, N. ; Lo, G.Q. ; Kwong, D.L. ; Li, Ming-Fu

Author_Institution

Dept. of Microelectron., Fudan Univ., Shanghai, China

Volume

32

Issue

4

fYear

2011

fDate

4/1/2011 12:00:00 AM

Firstpage

461

Lastpage

463

Abstract

In this letter, we report for the first time the impact of gate dielectric geometry on gate tunneling in a cylindrical-gate (CG) nanowire (NW) transistor. An analytical 2-D gate tunneling model is developed and used to assess quantitatively the tunneling probability in the CG NW transistor. A reduction in gate tunneling probability is predicted in the CG NW transistor compared with a planar-gate (PG) transistor with the same dielectric thickness. This effect can be very significant when the dielectric curvature is large as in practical NW devices. A high- k gate dielectric is more effective in suppressing the gate tunneling in CG transistors than in PG transistors.

Keywords

MOSFET; high-k dielectric thin films; nanoelectronics; nanowires; semiconductor quantum wires; tunnelling; 2D gate tunneling model; cylindrical-gate nanowire transistor; dielectric thickness; gate dielectric geometry; high-k gate dielectric; nanowire MOSFET; tunneling probability; Approximation methods; Dielectrics; Logic gates; MOSFETs; Silicon; Tunneling; 1-D/2-D tunneling; Cylindrical gate (CG); WKB approximation; high-$k$; nanowire (NW) transistor;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2107499

Filename

5725159