Low power with high stability 12T MTCMOS based SRAM cell for write operation

This paper focuses on the power dissipations at different supply voltages, bit line capacitances and stability analysis at different pull-down ratios of a novel low power 12T MTCMOS SRAM cell. Because of MTCMOS technology, the SRAM cell is having low VT (LVT) transistors and there are two high VT (HVT) Sleep transistors as well. Sleep transistors and a LVT Transmission gate (TG) in conjunction are used for reducing the wake up power during transition from sleep mode to active mode and sleep power during transition from sleep mode to active mode for writing operations of the SRAM cell. This reduces the static energy dissipation of the cell. In the proposed structure two additional voltage sources are also used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines. The reduction in swing causes the reduction in dynamic power dissipation. Because of very low leakage currents in MTCMOS technology, the stability of data retention is also enhanced. Simulation results of power dissipation and stability of the proposed SRAM cell have been determined and compared with those of some other exiting models of SRAM cell. The proposed cell dissipates less power at different supply voltages, bit line capacitance and better stability at different pull-down ratios than the other SRAM models. Simulation has been done in 45nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose.