Title :
An improved drain-current-conductance method with substrate back-biasing
Author :
Tan, C.B. ; Chim, W.K. ; Chan, D.S.H. ; Lou, C.L.
Author_Institution :
Chartered Semicond. Manuf. Ltd., Singapore
fDate :
2/1/1999 12:00:00 AM
Abstract :
A previously developed drain-current-conductance method (DCCM) is extended to investigate the effect of back-bias on LATID NMOSFETs. For the same effective gate overdrive, the extracted drain and source series resistances increase as the back-bias is increased. Two-dimensional device simulation showed that the increased back-bias results in reduced current contour values at the drain/source regions as a result of the increase in the series resistances
Keywords :
MOSFET; LATID NMOSFET; current contour; drain current conductance method; parameter extraction; series resistance; substrate back bias; two-dimensional device simulation; Circuit synthesis; Earth Observing System; Electrostatic discharge; Fingers; Immune system; MOSFET circuits; Predictive models; Protection; Scalability; Silicon on insulator technology;
Journal_Title :
Electron Devices, IEEE Transactions on
