• DocumentCode
    1467214
  • Title

    1.3 V single-stage CMOS opamp

  • Author

    Lu, G.N. ; Sou, G.

  • Author_Institution
    Lab. des Instrum. et Syst., Univ. Pierre et Marie Curie, Paris, France
  • Volume
    34
  • Issue
    22
  • fYear
    1998
  • fDate
    10/29/1998 12:00:00 AM
  • Firstpage
    2073
  • Lastpage
    2074
  • Abstract
    A low-voltage, single-stage opamp realised using a conventional CMOS process is proposed. It was designed by using novel regulated-cascode transistors which have a lower output compliance voltage. A gain-enhancement active load has been built by using a bias-stabilising technique. It enables the opamp to achieve a DC gain of >68 dB with a reduction in supply voltage to ~1.3 V
  • Keywords
    CMOS analogue integrated circuits; low-power electronics; operational amplifiers; 1.3 V; 68 dB; DC gain; active load; bias stabilisation; low-voltage single-stage CMOS opamp; output compliance voltage; regulated-cascode transistor;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19981436
  • Filename
    741289
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1467214