A 45-ns 16-m It Dram With Triple-well Structure

Author

Fujii, Syuso ; Ogihara, Masaki ; Shimizu, Mitsuru ; Yoshida, Munehiro ; Numata, Kenji ; Hara, Takahiko ; Watanabe, Shigeyoshi ; Sawada, Shizuo ; Mizuno, Tomohisa ; Kumagai, Junpei ; Yoshikawa, Susumu ; Kaki, Seiji ; Saito, Yoshikazu ; Aochi, Hideaki ; Ham

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1170

Lastpage

1175

Abstract

A 16-Mbit DRAM fabricated with a 0.6- mu m triple-well CMOS technology on an n-substrate is described. The fast RAS access time of 45 ns has been achieved by the use of a triple-well structure, an optimized chip architecture, and a decoded word-line bootstrap driver. An advanced trench capacitor cell of area 4.8 mu m² is realized by introducing a quarter-pitched memory array arrangement. A three-way voltage-down conversion system enhances RAM performance as well as reliability. The RAM measures 7.87*17.4 mm².

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 0.6 micron; 16 Mbit; 45 ns; 7.87 to 17.4 mm; CMOS technology; DRAM; RAS access time; decoded word-line bootstrap driver; dynamic RAM; n-substrate; optimized chip architecture; performance; quarter-pitched memory array arrangement; reliability; three-way voltage-down conversion system; trench capacitor cell; triple-well structure; CMOS technology; Capacitors; Circuits; Decoding; MOS devices; MOSFETs; Power supplies; Power system reliability; Random access memory; Read-write memory; Semiconductor device measurement; Variable structure systems; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572574

Filename

572574