A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads

A 25-ns 4-Mbit CMOS SRAM with 512 K word*8-bit organization has been developed. The RAM was fabricated using a 0.5- mu m double-poly and double-aluminum CMOS technology and was assembled in a 32-pin 400-mil DIP. A small cell size of 3.6*5.875 mu m² and a chip size of 7.46*17.41 mm² were obtained. A fast address access time of 25 ns with a single 3.3-V supply voltage has been achieved using the newly developed dynamic bit-line load (DBL) circuit scheme incorporated with an address transition detector (ATD), divided word-line structure (DWL), three-stage sense amplifier, and low-noise output circuit approach. A low operating current of 46 mA at 40 MHz and low standby currents of 70 mu A (TTL) and 5 mu A (CMOS) were also attained.