An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell

Author

Momodomi, Masaki ; Itoh, Yasuo ; Shirota, Riichiro ; Iwata, Yoshihisa ; Nakayama, Ryozo ; Kirisawa, Ryouhei ; Tanaka, Tomoharu ; Aritome, Seiichi ; Endoh, Tetsuo ; Ohuchi, Kazunori ; Masuoka, Fujio

Author_Institution

ULSI Res. Center, Toshiba Corp., Kawasaki, Japan

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1238

Lastpage

1243

Abstract

A 5-V-only high-density (512 K*8 bit) electrically erasable and programmable read-only memory (EEPROM) has been designed and fabricated by using a NAND-structured cell with 1.0- mu m design rules. The average cell area per bit is 12.9 mu m². Block erasing, successive programming, and random reading are achieved using a newly developed NAND-cell control circuit. Typical erasing time is 1.0 ms and page-programming time is 4.0 ms, equivalent to 1.0 mu s/bit. A dynamic sensing system is introduced to sense the small cell current. Typical read access time is 1.6 mu s. The die size is 10.7*15.3 mm².

Keywords

CMOS integrated circuits; EPROM; VLSI; integrated circuit technology; integrated memory circuits; 1 micron; 1.6 mus to 4 ms; 10.7 to 15.3 mm; 4 Mbit; 5 V; 512 kbyte; CMOS; EEPROM; NAND-structured cell; block erasing; cell area per bit; die size; dynamic sensing system; erasing time; page-programming time; random reading; read access time; successive programming; Associate members; Character generation; Circuits; EPROM; Flash memory; Helium; Manufacturing; Nonvolatile memory; PROM; Ultra large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572587

Filename

572587