DocumentCode
1467331
Title
120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs
Author
Terada, Yasushi ; Kobayashi, Kazuo ; Nakayama, Takeshi ; Hayashikoshi, Masanori ; Miyawaki, Yoshikazu ; Ajika, Natsuo ; Arima, Hideaki ; Matsukawa, Takayuki ; Yoshihara, Tsutomu
Author_Institution
LSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Itami, Japan
Volume
24
Issue
5
fYear
1989
fDate
10/1/1989 12:00:00 AM
Firstpage
1244
Lastpage
1249
Abstract
A 1-Mbit CMOS full-featured EEPROM using a 1.0- mu m triple-polysilicon and double-metal process is described. The design is aimed at developing a manufacturable 120-ns 1-Mbit EEPROM with small chip size. Therefore, an advanced memory cell with high read current, an improved differential sensing technique, and an efficient ECC scheme are developed. The differential sensing amplifier utilizes the output of a current sensing amplifier connected to unselected memory as a reference level. The cell size is 3.8*8 mu m2 and the chip size is 7.73*11.83 mm2. The device is organized as either 128 K*8 or 64 K*16 by via-hole mask options. A 256-byte/128-word page-mode programming is implemented.
Keywords
CMOS integrated circuits; EPROM; VLSI; integrated circuit technology; integrated memory circuits; 1 Mbit; 1 micron; 128 kbyte; 16 bit; 3.8 to 8 micron; 7.73 to 11.83 micron; CMOS; ECC scheme; EEPROM; cell size; chip size; current sensing amplifier; differential sensing amplifier; differential sensing technique; double-metal process; high read current; page-mode programming; triple-polysilicon; CMOS process; Circuits; Differential amplifiers; EPROM; Error correction codes; Manufacturing; Nonvolatile memory; Random access memory; Sea measurements; Space vector pulse width modulation;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1989.572588
Filename
572588
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