Title :
A 23-ns 256 K EPROM with double-layer metal and address transition detection
Author :
Hoff, David ; Pathak, Saroj ; Payne, James ; Shrivastava, Ritu ; Arreola, Jose I. ; Norris, Christopher ; Tsao, Shou-Chang ; Prickett, Bruce L. ; Orput, Matthew
Author_Institution :
Cypress Semicond. Corp., San Jose, CA, USA
fDate :
10/1/1989 12:00:00 AM
Abstract :
A 23-ns 256 K CMOS EPROM has been developed on a 0.8- mu m double-layer metal technology. The product employs a differential configuration and an interleaved FAMOS cell with a high read current of 80 mu A at Vg=4 V, Vd=1.5 V, 25 degrees C. The array is organized as 32 K*8. Fast access time is obtained by a combination of advanced technology, double-layer metal (DLM), differential sensing, address transition detection (ATD), and a ground-switched decoding scheme. DLM is used to strap word lines. High performance is obtained by reducing bit-line length to 256 cells, with 2048 cells per word line. The combination of strapped word lines along with short bit lines produces very fast access time. The active power is 75 mA, and standby power is 9 mA at room temperature. The die size is 116*339 mil2 (25.4 mm2).
Keywords :
CMOS integrated circuits; EPROM; VLSI; integrated circuit technology; integrated memory circuits; 0.8 micron; 116 to 339 mil; 23 ns; 256 K; 256 kbit; 32 kbyte; 75 mA; 9 mA; CMOS; DLM; EPROM; access time; active power; address transition detection; die size; differential sensing; double-layer metal; ground-switched decoding scheme; interleaved FAMOS cell; read current; room temperature; short bit lines; standby power; strapped word lines; CMOS technology; Circuits; Decoding; Delay; EPROM; Packaging; Reduced instruction set computing; Silicides; Strips; Temperature;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1989.572589
