Title :
A 54000-gate ECL array with substrate power supply
Author :
Kokado, Masayuki ; Yoshida, Makoto ; Miyoshi, Norihito ; Suzuki, Kouichi ; Takaoka, Matsuo ; Tsuzuki, Norihisa ; Harada, Hideki
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
fDate :
10/1/1989 12:00:00 AM
Abstract :
A sub-100-ps, 54000-gate ECL array with substrate power supply has been developed on a 64-mm2 die. Gate density of 1160 gate/mm2 is achieved by the newly developed ´CUBE´ (Chip with Upside and Backside Electrodes) technology which enables a five-layer interconnection structure including heavily doped substrate and a polycide layer in addition to the conventional three metal layers. Gate delay of 96 ps with 2.4-mW power dissipation is obtained using double-polysilicon self-aligned transistor technology. The features of this technology are (1) high-density LSI resulting in improved interconnection delay and smaller chip size, (2) small voltage drops of power supply on the chip, and (3) an increased number of signal pads by eliminating VEE pads from the top side of the chip.
Keywords :
VLSI; bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; logic arrays; 2.4 mW; 96 ps; CUBE; Chip with Upside and Backside Electrodes; features; five-layer interconnection structure; heavily doped substrate; high-density LSI; interconnection delay; polycide layer; power dissipation; self-aligned transistor technology; signal pads; small voltage drops; substrate power supply; three metal; Aluminum; Delay; Electrodes; Integrated circuit interconnections; Large scale integration; Power dissipation; Power supplies; Resistors; Tungsten; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1989.572593
